Let MindShare Bring "Hands-On PCI Express 3.1" to Life for You MindShare's PCI Express System Architecture course starts with a high-level view of the design to provide the big-picture context and then drills down into the details for each part of the design, providing a thorough understanding of the hardware and software protocols. This course describes additional features added to the architecture when moving from PCIe specification revision 1.1 to 2.0 to 2.1 to 3.0 and 3.1 . PCIe 3.0 (Gen 3) doubles the bandwidth available in revision 2.0 (Gen 2) by increasing the transfer rate and dropping 8b/10b encoding. But a number of protocol changes were also implemented in the change from revision 2.0 to 2.1, and those are described, too. The Gen 3 changes are physical layer updates to support the higher speed and some new steps that were needed for link training to get that speed working reliably, but the upper layers are left unchanged. MindShare Courses On PCI Express 3.1, 2.x and 1.x as well as Mobile-PCI Express:
All of MindShare's classroom and virtual classroom courses can be customized to fit the needs of your group. Hands-On PCI Express 3.1 Course Info PCI Express features and capabilities The definition and responsibilities of each of the layers in the interface How hardware-based automatic error detection and correction mechanism works The various additional levels of error detection and reporting The details of the packet-based protocol used by PCIe The address space and packet-routing methods used How the various power management techniques work Configuration register details that provide control and status visibility to software What are some ECNs related to PCI Express 2.1 and 3.1 specification What changes are needed to run the link at 8.0GT/s (rev 3.0 speeds) This course is hardware-oriented, but is suitable for both hardware and software engineers because the configuration registers used to control the hardware are covered in detail.
The course is ideal for RTL-, chip-, system- or system board-level design engineers who need a broad understanding of PCI Express. Because the course contains practical examples of transactions on the various bus interfaces, the course is also suitable for chip-level and board-level validation engineers. PCI Architecture Background Foundation PCI Legacy Configuration Transaction Generation PCI Express Features and Architecture Overview TLP, DLLP and Ordered Set Packet Format Overview Legacy and Enhance Configuration Transaction Generation Header 0/1, Capability and Extended Capability Register Overview Scan your system and determine topology Address Space and Transaction Routing Debug problem with plug-and-play address mapping Quality of Service and Arbitration TC/VC Mapping and VC/Port Arbitration Runtime Flow Control Update Mechanism Simplified ordering table (2.1) Examples of Variety of Error Scenarios Nullified Packets and Store-and Forward vs. Cut-Through Mode
Physical Layer Logic (Gen1/Gen2) Physical Layer Logic (Gen3) Physical Layer Electrical (Gen1/Gen2/Gen3) Link Initialization & Link Training Detect, Polling, Configuration, L0, Recovery (Retraining) States Power Management States: L0, L0s, L1, L1 Active, L2, L3 Power States Link Width and Speed Changing Error Detection and Handling Correctable, Non-Fatal and Fatal Errors Determine source and error reporting mechanism Software controlled Power Management Active Hardware-based Power Management Optimized Buffer Flush Fill (OBFF) (2.1), Latency Tolerance Reporting (2.1) and L1 sub-states (3.1) Investigate source of MSI interrupt and delivery Fundamental Reset (Cold and Warm Reset), In-band Reset (Hot Reset) Function Level Reset (FLR) Hot Plug and Power Budgeting Dynamic Power Allocation (2.1) 2.1 and 3.1 ECN as required such as: Process Address Space ID A basic understanding of digital bus architectures such as PCI is highly recommended.
1) MindShare will supply a copy of the "PCI Express Technology" eBook (covers PCIe 3.0) MindShare’s textbook (PCIe 3.0) Authors: Mike Jackson and Ravi Budruk Available through the MindShare Store and major bookstore outlets. 2) Downloadable PDF version of the presentation slides 3) MindShare Arbor software tool, used for student labs in the class 4) Optional Comprehensive PCI Express 3.1 eLearning course (discounted pricing applies) 5) Optional Introduction to PCI Express IO Virtualization eLearning course (discounted pricing applies)Synopsys’ complete, silicon-proven DesignWare® IP for PCI Express® (PCIe®) solution includes a suite of digital controllers, PHYs, and verification IP, all of which are designed to the PCIe 4.0, 3.1, 2.1 and 1.1 (Gen4, Gen3, Gen2, Gen1) and PIPE specifications. In addition, Synopsys supports the M-PCIe™ ECN with silicon-proven M-PHY and M-PCIe Controller IP. As the leading supplier of PCIe IP, Synopsys’ DesignWare IP for PCIe® has gone through extensive third-party interoperability testing with products shipping in volume production.
The strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk for next-generation mobile, consumer, communication, enterprise, IoT and automotive system-on-chips (SoCs). PCI Express to AHB Bridge PCI Express to AXI Bridge Single Root I/O Virtualization IP PCIe 4.0 PHY IP PCIe 2.1 PHY IP IP Virtualizer Development Kits PCIe 3.1 PHY IP PCIe 1.1 PHY IP Broad portfolio including Endpoint, Dual Mode, Root Port, and Switch/Bridgelow latency and low gate count Powers the Agilent and PCI-SIG protocol test card Largest installed base of all PCI Express IP providers Designed for integration of both upstream and downstream applications as well as PCI Express bridges and switches Fully compliant with the PCI Express 3.x (8 GT/s), 2.x (5.0 GT/s), and 1.x (2.5 GT/s) as well as the PHY interface for PCIe 3.x (PIPE4 draft 6) (8-bit, 16-bit and 32-bit) specifications