Compilation Pipe
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Compilation Pipe
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The GCC 4.1.2 documentation has this to say about the -pipe option:
Use pipes rather than temporary files for communication between the various stages of compilation. This fails to work on some systems where the assembler is unable to read from a pipe; but the GNU assembler has no trouble.
I assume I'd be able to tell from error message if my systems' assemblers didn't support pipes, so besides that issue, when does it matter whether I use that option? What factors should go into deciding to use it?
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It has + and - considerations. Historically, running the compiler and assembler simultaneously would stress RAM resources.
Gcc is small by today's standards and -pipe adds a bit of multi-core accessible parallel execution.
But by the same token the CPU is so fast that it can create that temporary file and read it back without you even noticing. And since -pipe was never the default mode, it occasionally acts up a little. A single developer will generally report not noticing the time difference.
Now, there are some large projects out there. You can check out a single tree that will build all of Firefox, or NetBSD, or something like that, something that is really big. Something that includes all of X, say, as a minor subsystem component. You may or may not notice a difference when the job involves millions of lines of code in thousands and thousands of C files. As I'm sure you know, people normally work on only a small part of something like this at one time. But if you are a release engineer or working on a build server, or changing something in stdio.h, you may well want to build the whole system to see if you broke anything. And now, every drop of performance probably counts...
In our experience with a medium-sized project, adding -pipe made no discernible difference in build times. We ran into a couple of problems with it (sometimes failing to delete intermediate files if an error was encountered, IIRC), and so since it wasn't gaining us anything, we quit using it rather than trying to troubleshoot those problems.
Trying this out now, it looks to be moderately faster to build when the source / build destinations are on NFS (linux network). Memory usage is high though. If you never fill the RAM and have source on NFS, seems like a win with -pipe.
Honestly there is very little reason to not use it. -pipe will only use a tad more ram, which if this box is building code, I'd assume has a decent amount. It can significantly improve build time if your system is using a more conservative filesystem that writes and then deletes all the temporary files along the way (ext3, for example.)
One advantage is that with -pipe will the compiler interact less with a file system. Even when it is a ram disk does the data still need to go through the block I/O and file system layers when using temporary files whereas with a pipe it becomes a bit more direct.
With files does the compiler first need to finish writing before it can call the assembler. Another advantage of pipes is that both, the compiler and assembler, can run at the same time and it is making a bit more use of SMP architectures. Especially when the compiler needs to wait for the data from the source file (because of blocking I/O calls) can the operating system give the assembler full CPU time and let it do its job faster.
From a hardware point of view I guess you would use -pipe to preserve the lifetime of your hard drive.
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Design Example - PHY Interface for PCI Express (PIPE)
Design Example - PHY Interface for PCI Express (PIPE)
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This article covers the steps required to succesfully instantiate the Phyical Layer (Gen 1 or Gen 2) of a PCIe Transceiver, including the PHY Interface for PCI Express (PIPE), on a Stratix V FPGA (For Quartus II v11.0 or v12.0sp2). It will be useful for users who want to quickly get a working PHY IP design up and running to view simulation results. The goal of the article is to briefly guide the user through the design, compilation, and simulation of the Altera generated PIPE reference design. After finishing the article, the reader will be able to:
This guide assumes the reader has standard knowledge of the use of Quartus and ModelSim.
For a general guide for designing a Trasnceiver using Altera Generated IP, see the Transceiver Design Flow Series .
Altera Transceiver PHY IP Core User Guide (PDF ) - This document describes configuration details for the PIPE (Useful when generating the IP from the MegaWizard)
Altera Stratix V Device Documentation - Transceiver Architecture, Clocking, Configurations and reset controller information.
ModelSim SE Command Reference (PDF ) - A guide to tcl commands and in ModelSim.
Quartus v12.0 b232 Altera PCIE PIPE Design File (ZIP) (Up-to-date) Contains everything you need to compile and simulate.
The table below lists the specifications for the Quartus version 11.0 build 157 design:
The table below lists the specifications for the Quartus version 12.0sp1 build 232 design:
The table below lists the specifications for the Quartus version 13.1 build 162 design:
The design implements the following blocks:
Please see figure 1-1 for a block diagram representing the components that make up the top level design file: top_pcie_pipe.v.
Figure 1-1: Top Level Block Diagram- PCI_Express_Top_Level_Block_Diagram.jpeg (Click here for image)
To view a larger version of the image, click on the image, then click on the image again once the new page loads, and then hold ctrl and scroll the mouse wheel to zoom in and out.
The Physical Layer imports 4 clocks: an input reference clock of 100 MHz, a fixed clock at 125 MHz, a management clock meant for the Avalon MM Interface of 150 MHz, and a reference clock for the frequency
checker. The input signal singal rate_switch_g1_to_g2_phase switches the PCIe configuration from Gen 1 to Gen 2.
Megawizard generated PCIe PHY IP. Please see the Altera Transceiver PHY IP Core User Guide (PDF) for more information.
Simple state machine that toggles the PIPE controls according to which state it is currently in.
This module gets the state transitions from pipe_state_mc and generates PIPE control signals and all the required controls for the data generator module.
Generates PIPE specific ordered sets corrseponding to the controls received from datagen_ctrl_top . This module instantiates datagen_16bit_x1 for 4 lanes. datagen_16bit_x1.v generates 16-bit data based on the controls received form datagen_ctrl_top.
PRBS 23 pattern generator whos output is fed to the pipe_txdata during DATA_PHASE. All lanes get the same PRBS data.
PRBS 23 pattern checker that verifies the looped back PRBS data on pipe_rxdata. There are two checkers because of the uncertainty in the byte order of pipe_rxdata. Depending on the sampling time of the Byte SERDES in the Rx PCS, pipe_rxdata either has bytes ordered correctly or incorrectly. We need to check for these two cases. Therefore, byte ordering is done earlier in this module to correct for possible misordering.
This module writes to/reads from the memory mapped registes inside of the Transceiver PHY IP through the Avalon PHY Management Interface (see the Avalon Specification for details). The Avalon-MM PHY management interface provides access to PIPE PCS and PMA features that are not part of the standard PIPE interface. This module is customized specifically for the PIPE. See the "Interfaces - Registers" section of chapter 6 of the Altera Transceiver PHY IP Core User Guide .
Assigns parallel txdata of PIPE PHY IP - either data from the data generator or PRBS data from the prbs generator - to the txdata lanes of the PHY IP.
There is a module that syncrhonizes the brd_reset to the phy_mgmt_clk.
There is a process that synchronizes tx_ready and rx_ready to the pipe_clk.
There is a process that handles byte ordering of the rxdata.
1) Download and unzip the zip files linked above into a folder to be used as the download directory.
2) Open the project file (.qpf) by going to File > Open Project and navigating to \SV_PIPE\source. Open top_pcie_pipe.qpf.
3) Use the Megawizard Plug-in Manager to generate Altera Generated IP (labeled in figure 1-1 )
Before compiling you must regenerate the Altera generated IP using the Megawizard. You will perform this step twice - once for the pcie_pipe_phy_ip.v and once for the top_reconfig.v . Open MegaWizard Plug-In Manager and choose edit a variation.
After the previous steps have been completed, you can compile the entire design by going to Processing > Start > Start Analysis and Synthesis.
4) During compilation you can expect following critical warnings
You will need to create a .tcl script called phy_sim_top.tcl (there already exists a fully working phy_sim_top.tcl in the zip that contains the project files, however you will need to modify it if you add your own design files) that contains compilation commands for:
Use the vlib command to create a design library. Use the following Tcl code as a reference:
vlib msim_pcie_pipe_phy_ip => creates a design library called msim_pcie_pipe_phy_ip in the current working directory.
Note that for ModelSim compilation, a vlog of the files is required before the vsim command. Use the vlog command to compile Verilog source code into a specified working library (or to the work library by default).
For example: vlog -work msim_pcie_pipe_phy_ip test.v => compiles the test.v file into the msim_pcie_pipe_phy_ip directory.
The - work Specifies a logical name or pathname of a library that is to be mapped to the logical library work. By default, the compiled design units are added to the work library. If a pathname is specified, the specified pathname overrides the pathname specified for work in the project file.
If compiling a System Verilog file (.sv), you must place the " -sv " command after the "vlog" command and before the name of the file to be compiled.
After writing commands to create necessary libraries and compile design units, use the vsim command to invoke the modelsim simulator. Use the " -c option to run the simulation in command line mode. The -novopt option resolves certain compatibility issues. -t sets the time scale to .The -L lets the simulator know where to look for design files when simulating.
Use this example script as a reference, and see this guide for a reference to using tcl commands in ModelSim.
The attached zip file has all the required design and simulation files. To start the simulation, launch Modelsim and source phy_sim_top.tcl
Annotated timing diagrams of the proper operation of the 6 states of pipe_state_mc are provided for your reference.
Figure 2-1 : INIT_PHASE_G1- P1_TO_P0_PHASE_G1_annotated.png (Click here for image)
Figure 2-2 : DATA_PHASE_G1- DATA_PHASE_G1_annotated.png (Click here for image)
Figure 2-3: RATE_SWITCH_G1_TO_G2_PHASE- RATE_SWITCH_G1_TO_G2_annotated.png (Click here for image)
Figure 2-4: P1_TO_P0_PHASE_G2- P1_TO_P0_PHASE_G2_annotated.png (Click here for image)
Figure 2-5: DATA_PHASE_G2- DATA_PHASE_G2_annotated.png (Click here for image)
Stratix V, PCIE PIPE PHY IP, Tranceiver Reconfiguration Controller, Physical layer, PCI Express, Express, Stratix Five, GT, GS, GX, Design, Example, guide, walkthrough,
PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files,
© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not
supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,
For more complete information about compiler optimizations, see our Optimization Notice .
PCIE PIPE PHY IP, Traceiver Reconfiguration Controller
PCIE PIPE PHY IP, Traceiver Reconfiguration Controller
PCIE PIPE PHY IP, Traceiver Reconfiguration Controller
cntr >= 0x051 && cntr <= 0x164 & rx_syncstatus_reg = 0xFF (receiver is synced)
cntr == 0x164 (wait 0x164 clock cycles)
Gen 1, P0, Electricle Idle de-asserted
pipe_phystatus_reg == 4'b1111 (rate switch from Gen 1 to Gen 2 succesful)
Gen 2, P1, Electricle Idle asserted
cntr >= 0x051 && cntr <= 0x164 & rx_syncstatus_reg = 0xFF
Gen 2, P0, Electricle Idle de-asserted, ready_for_mgmt = 1
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