Yokoyama Natsuki
🔞 ALL INFORMATION CLICK HERE 👈🏻👈🏻👈🏻
Yokoyama Natsuki
All Titles TV Episodes Celebs Companies Keywords Advanced Search
Fully supported English (United States) Partially supported Français (Canada) Français (France) Deutsch (Deutschland) हिंदी (भारत) Italiano (Italia) Português (Brasil) Español (España) Español (México)
Up
453,175
this week
Contribute to IMDb. Add a bio, trivia, and more.
Update information for Natsuki Yokoyama »
Biography
Awards
Photo Gallery
Filmography (by Job)
Trailers and Videos
Filmography
by Year
by Job
by Ratings
by Votes
by Genre
by Keyword
Personal Details
Biography
Other Works
Publicity Listings
Official Sites
Contact Info (IMDbPro)
Did You Know?
Personal Quotes
Trivia
Trademark
Photo & Video
Photo Gallery
Trailers and Videos
Opinion
Awards
Related Items
Credited With
News
External Sites
Professional Services
Get more at IMDbPro
How Much Have You Seen?
How much of Natsuki Yokoyama's work have you seen?
Kill la Kill
Animation Department
Mob Psycho 100
Animation Department
Corpse Princess: Aka
Animation Department
Lupin the Third: The Woman Called Fujiko Mine
Animation Department
Show all
Hide all
|
Show by...
Job
Year »
Rating »
Number of Ratings »
Genre »
Keyword »
|
Edit
Hide
Show
Animation department (14 credits)
2019
Saga of Tanya the Evil - The Movie
(second key animator)
2016
Dou Kyu Sei: Classmates
(key animator)
- Nikumi kirenai roku denashi
(2013)
... (key animator)
- Kizetsu suru hodo nayamashî
(2013)
... (key animator)
- Prison of Love
(2012)
... (key animator)
2011
Wish Upon the Pleiades
(TV Series) (key animator)
- Hoshi wa tôku
(2009)
... (animator)
- Shi ga mau
(2008)
... (inbetween artist: Gainax)
2004
Gunbuster 2: Diebuster
(Video short) (inbetween artist)
Check out some of our favorite LGBTQIA+ couples in Hollywood.
IMDb's guide to the most anticipated new and returning TV shows coming this fall.
Take a look at some of the famous twins of Hollywood, including Cole and Dylan Sprouse , Mary-Kate and Ashley Olsen , and more.
All Books Conferences Courses Journals & Magazines Standards Authors Citations
Department of Power Electronics Systems Research
Biography Natsuki Yokoyama received the M.S. degree from Waseda University, Tokyo, Japan, in 1983. In 1983, he joined the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan and started his work on multilevel interconnect technologies for LSI's. From 1991 to 1998, he was engaged in the development of high-density DRAM's. After then, he moved to process integration technology for CMOS, and CMOS embedded with MEMS sensors. Recently, his research focuses on the development of SiC power devices.,Mr. Yokoyama is a member of the Electrochemical Society and the Japan Society of Applied Physics. (Based on document published on 6 December 2010).
N. Yokoyama (13) Natsuki Yokoyama (6) T. Kisu (6) H. Yamashita (6) R. Nagai (4) Show More…
Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan (8) Central Research Laboratory, Hitachi and Limited, Tokyo, Japan (6) Hitachi VLSI Engineering Corporation Limited, Kodaira, Tokyo, Japan (3) Kabushiki Kaisha Hitachi Seisakusho, Chiyoda-ku, Tokyo, JP (3) Hitachi Ltd., Tokyo, Japan (2) Show More…
IEEE Transactions on Electron Devices (4) IEEE Journal of Solid-State Circuits (2) 1992 Symposium on VLSI Technology Digest of Technical Papers (1) 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers (1) 1996 Symposium on VLSI Technology. Digest of Technical Papers (1) Show More…
Honolulu, HI, USA (3) San Francisco, CA, USA (2) Hiroshima, Japan (1) Jeju, Korea (South) (1) Seattle, WA, USA (1) Show More…
silicon compounds (6) DRAM chips (5) wide band gap semiconductors (4) MOSFET (3) Monte Carlo methods (3) Show More…
Year: 2014 | Conference Paper | Publisher: IEEE
We investigated how to reduce the energy loss of server power supplies equipped with vertical-trench normally-off Silicon Carbide junction-gate field-effect transistors (SiC-JFETs). High-speed driving circuits consisting of a speed-up capacitor with separated source terminal and timing adjust circuits to ensure a dead time margin are proposed. Applying the developed normally-off SiC-JFETs and the ... Show More
Year: 2014 | Conference Paper | Publisher: IEEE
Year: 2014 | Conference Paper | Publisher: IEEE
The SiC JFET/Si MOSFET cascode is an attractive alternative to conventional Si MOSFETs or IGBTs due to its low on-resistance and good switching performance. However, dv/dt control without increased switching loss is difficult when using a conventional gate resistor or capacitor for the MOSFET. In this paper, a dv/dt and switching loss control method that ensures a good switching performance for th... Show More
Year: 2014 | Conference Paper | Publisher: IEEE
Year: 2011 | Volume: 58, Issue: 2 | Journal Article | Publisher: IEEE
A 2-D model of aluminum-ion implantation into 4H-SiC (0001) was developed and assessed through reverse current IR-voltage VR characteristics of p-n diodes. The model was based on a Monte Carlo simulation using a binary-collision approximation. For a moderate dose (1011 - 1013 cm-2), simulated isoconcentration contours were independent of the orientation of the masking edge. This condition allowed ... Show More
Year: 2011 | Volume: 58, Issue: 2 | Journal Article | Publisher: IEEE
Year: 2009 | Volume: 56, Issue: 5 | Journal Article | Publisher: IEEE
Forward current density (JF)-forward voltage (VF) characteristics are experimentally and computationally investigated for 4H-silicon carbide junction barrier Schottky (JBS) diodes with a lightly doped (3 - 5 times1015 cm-3) drift layer and 2-mum-wide p+ stripe regions separated by 1 mum. The JF-VF characteristics of fabricated JBS diodes are compared with those of Schottky barrier diodes simultane... Show More
Year: 2009 | Volume: 56, Issue: 5 | Journal Article | Publisher: IEEE
Year: 2008 | Volume: 55, Issue: 8 | Journal Article | Publisher: IEEE
This paper presents a detailed analysis and precise modeling of multiple-energy Al implantations necessary for boxlike profiles in the p+-region of 4H-SiC power devices. To demonstrate the balance between "scatter-in channeling" and "amorphization-suppressed channeling," a thin-surface SiO2 layer is formed on 4H-SiC substrates misoriented by 8deg from (0001) toward [112 macr0]. Experimental, as we... Show More
Year: 2008 | Volume: 55, Issue: 8 | Journal Article | Publisher: IEEE
Year: 2007 | Conference Paper | Publisher: IEEE
A highly efficient inverter was achieved by using normally-off SiC-JFETs (silicon carbide junction FETs) as switching devices. A precise control system for the gate voltage and the high-speed driver circuit are quite important issues in the realization of an inverter system for operating JFETs with threshold voltage lower than 2V and for the reduction of switching loss. A two step push-pull circui... Show More
Year: 2007 | Conference Paper | Publisher: IEEE
Year: 2005 | Volume: 1 | Conference Paper | Publisher: IEEE
A surface micromachined capacitive pressure sensor was fabricated using conventional back-end of line (BEOL) processes in a standard CMOS fabrication line. The combination of standard interlayer dielectric and tungsten was used as sacrificial layers and electrodes, which achieves a large etching selectivity in sacrificial layer removal processes. Measured dependences of capacitance on applied pres... Show More
Year: 2005 | Volume: 1 | Conference Paper | Publisher: IEEE
Year: 2002 | Volume: 49, Issue: 12 | Journal Article | Publisher: IEEE
Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, namely, to 0.4 nm (rms). A strained-Si layer was then successfully grown on the CMP-treated SiGe substrate. The fabricated strained-Si MOSFETs showed good t... Show More
Year: 2002 | Volume: 49, Issue: 12 | Journal Article | Publisher: IEEE
Year: 2001 | Conference Paper | Publisher: IEEE
Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ~1.5 MV/cm.... Show More
Year: 2001 | Conference Paper | Publisher: IEEE
Year: 2001 | Conference Paper | Publisher: IEEE
Thin films with high dielectric constant (high-/spl kappa/) have been attracting much attention because of their potential use as alternative gate dielectrics for sub-100 nm MOSFETs. In this paper we investigated the nature of mobility degradation due to the fixed charge for Al/sub 2/O/sub 3/ high-/spl kappa/ gate dielectric. We successfully recovered the mobility to half that of SiO/sub 2/ withou... Show More
Year: 2001 | Conference Paper | Publisher: IEEE
Year: 2000 | Conference Paper | Publisher: IEEE
A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped Si/sub x/Ge/sub 1-x/ as a gate material, the adequate threshold voltage of FD-SOI was realized. Show More
Year: 2000 | Conference Paper | Publisher: IEEE
Year: 1998 | Conference Paper | Publisher: IEEE
A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor el... Show More
Year: 1998 | Conference Paper | Publisher: IEEE
Year: 1998 | Volume: 11, Issue: 1 | Journal Article | Publisher: IEEE
The pretreatment process used in semiconductor manufacturing can include over one-hundred processes, and about 90% of the wafer transfers are done between processors or process chambers that have different ambient conditions from each other; that is, between the atmosphere and a vacuum ambient or between a low and a high vacuum ambient. The throughput and yield from a semiconductor manufacturing l... Show More
Year: 1998 | Volume: 11, Issue: 1 | Journal Article | Publisher: IEEE
Year: 1996 | Conference Paper | Publisher: IEEE
A ferroelectric memory cell with an area of only 7.03 /spl mu/m/sup 2/ designed with a 0.5-/spl mu/m rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and t... Show More
Year: 1996 | Conference Paper | Publisher: IEEE
Year: 1995 | Volume: 30, Issue: 11 | Journal Article | Publisher: IEEE
A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also elimi... Show More
Year: 1995 | Volume: 30, Issue: 11 | Journal Article | Publisher: IEEE
Year: 1994 | Conference Paper | Publisher: IEEE
In keeping with the trend of reducing DRAM cell area, with a target for 1-gigabit DRAMs of less than 0.3 /spl mu/m/sup 2/, the authors have developed a 0.29-/spl mu/m/sup 2/ metal/insulator/metal crown-shaped capacitor (MIM-CROWN) cell with low height by using 0.16-/spl mu/m process technologies.<> Show More
Year: 1994 | Conference Paper | Publisher: IEEE
Year: 1993 | Conference Paper | Publisher: IEEE
The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications. A subthreshold-current limiting scheme for word drivers is shown. The scheme uses a pMOS switching transistor between the wordline voltage and the driver transistor common-source terminal. The subthreshold current of a 256-Mb DRAM is reduced to 3% by applying this scheme to word drivers and decoders... Show More
Year: 1993 | Conference Paper | Publisher: IEEE
Year: 1993 | Volume: 28, Issue: 11 | Journal Article | Publisher: IEEE
256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces m... Show More
Year: 1993 | Volume: 28, Issue: 11 | Journal Article | Publisher: IEEE
Year: 1992 | Conference Paper | Publisher: IEEE
The fabrication of fine contact metallization down to 0.08 mu m in diameter for future 0.1- mu m-level ULSIs is discussed, and the electrical characteristics are evaluated. A two-layered etch mask, PMMA/poly-Si, was used for electron-beam delineation. Low-temperature dry etching permits the accurate patterning of the poly-Si layer in accordance with the PMMA mask, by increasing the PMMA etch-rate ... Show More
Year: 1992 | Conference Paper | Publisher: IEEE
IEEE Account
Change Username/Password
Update Address
Purchase Details
Payment Options
Order History
View Purchased Documents
Need Help?
US & Canada: +1 800 678 4333
Worldwide: +1 732 981 0060
Contact & Support
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2022 IEEE - All rights reserved.
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity. © Copyright 2022 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
Hitachi, Ltd. · Research and Development Group
A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more
We investigated 4H-SiC trench junction barrier Schottky (JBS) diodes from the viewpoints of the tradeoff between the electric field at the Schottky contact interface (E s) and the forward voltage drop, the effect on reduction of reverse leakage current, and the device yield. By calculating E s, we found that the trench JBS structure can make E s on...
A 3.3-kV SiC-Si hybrid module, composed of a low-forward-voltage (VF) SiC junction-barrier-Schottky (JBS) diode and a low-saturation-voltage VCE(sat) Si trench IGBT was fabricated and demonstrated highly efficient operation.
We fabricated trench Junction Barrier Schottky (JBS) diodes, and investigated the effect on the reduction of leakage current and the device yield. First, by calculating of electric field at the Schottky contact interface (Es), we found that the trench JBS structure can reduce Es one digit smaller than the planar JBS structure, setting 80o < The bev...
A silicon-carbide (SiC) junction field-effect transistor (JFET)/Si metal-oxide-semiconductor field-effect transistor (MOSFET) cascode is a good solution owing to its high reliability, low on-resistance, high switching speed, and good gate controllability. A 3.3 kV SiC vertical JFET using a double channel doping technique is proposed in this paper....
The SiC JFET/Si MOSFET cascode is an attractive alternative to conventional Si MOSFETs or IGBTs due to its low on-resistance and good switching performance. However, dv/dt control without increased switching loss is difficult when using a conventional gate resistor or capacitor for the MOSFET. In this paper, a dv/dt and switching loss control metho...
We investigated how to reduce the energy loss of server power supplies equipped with vertical-trench normally-off Silicon Carbide junction-gate field-effect transistors (SiC-JFETs). High-speed driving circuits consisting of a speed-up capacitor
Nsfw Asian Gif
Mature Nl
E621 Net Animated