Opinion: PPC, 68080 and other [660 comments]
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Opinion: PPC, 68080 and other [660 comments] pix (last poster: hammer) Amiga scene Not wanting to start a flame war with my first post on this board, but I'm hoping to get some solid opinion on the best Amiga hardware direction to take. For where I am coming from, after experimenting with various Amiga offerings over the years, emulation options are a given. Love digital...
English Amiga Board > Main > Amiga scene
hammer
Location: Sydney/Australia
#641 Posted on: 16 July 2025, 01:55
Quote:
Originally Posted by pandy71RP2040's PCIe would need to be upgraded for newer PCIe versions (lower latency), or improve RP2040's ARM Cortex M0+ @ 133 MHz with ARM Cortex A76 or higher e.g. Cortex A78C.PCIe (started with PCI) is one side of problem, another one is internal CPU latency - inability to interact with GPIO in time comparable to cycle time - this is why some vendors adding IO coprocessor or separate processor optimized to IO operation - TI has very flexible Programmable Real Time Unit and it can provide low latency https://www.ti.com/lit/sprace8 (approx 10 times lower than remaining CPU SoC) - also XMOS https://www.xmos.com/ provide solutions to achieve low latency front end for fast CPU - if you separate both then you gain possibility to use SoC's other than Broadcom (still lacking full documentation - for example video core is closed documentation).
Using PCIe or USB in isochronous mode probably will be time consuming but having multiple core CPU's this should be not a problem - you can dedicate single or two cores only to deal with isochronous mode.
RP2040 is the 1st attempt to remove middleman Broadcom SoC IP dependency.
@ https://www.ti.com/lit/sprace8
Ti AM335x Sitara SoC has ARM Cortex A8 up to 1 Ghz, which doesn't replace RPi 3A to 4B / CM4. https://www.ti.com/product/AM3358
Reminder, Buffee / TF1200 project uses Ti AM3358 with Cortex A8 @ 1 Ghz inside OSD3358 system on package.
The goal after RPi 4B / CM4 is to be better than ARM Cortex A72 while maintaining GPIO performance, not with a lower-tier Buffee / TF1200. The supply for RPi 3A+ / 3B and 4B / CM4 is not the issue.
RPi 3A+ Emu68 has no problems passing Buffee's Ti AM3358.
RPi 5 with RP2040 attached GPIO seems to be the transition phase towards RPi fat SoC attached GPIO.
Last edited by hammer; 16 July 2025 at 03:56.
Location: Hastings, New Zealand
#642 Posted on: 16 July 2025, 06:22
Quote:
Originally Posted by hammer4B/CM4 seems to be good enough. Why go further?The goal after RPi 4B / CM4 is to be better than ARM Cortex A72 while maintaining GPIO performance, not with a lower-tier Buffee / TF1200. The supply for RPi 3A+ / 3B and 4B / CM4 is not the issue.
RPi 3A+ Emu68 has no problems passing Buffee's Ti AM3358.
hammer
Location: Sydney/Australia
#643 Posted on: 16 July 2025, 06:55
Quote:
Originally Posted by Bruce Abbott1. During the 16-bit era, the Amiga 500 kept up with mainstream game consoles with the 68000 selection e.g. Sega Mega Drive/ Genesis.4B/CM4 seems to be good enough. Why go further?
During the 32-bit era, 68EC020 to 68030 wasn't on par with low-cost ($15 to $20) MIPS 3050 (R3000A with embedded MMU). MIPS 3050 is a poor man's 68LC040-like 1 IPC CPU solution.
On the CPU front in modern times, RPi 4B or CM4's ARM Cortex A72 slightly exceeds Nintendo Switch 1's ARM Cortex A57. Both Cortex A72 and Cortex A57 are three-issue wide ARMv8A CPU designs. With PiStorm32 with CM4 or 4B, the CPU selection slightly exceeds a mainstream game console's CPU selection.
Switch 2 has moved to ARM Cortex A78C, which is a four-issue wide ARMv8.x CPU design.
RPi 5's Cortex-A76 is a four-issue wide ARMv8.x CPU design.
Wedge Amigas are in the cheap RISC camp's price range, not with the PowerMac wannabe i.e. workstation-priced RISC. For this topic, Amiga Hombre (PA-RISC clone) was in the cheap RISC camp's price range. Again, Amiga is not a Mac, which is a failure for Phase 5 / Escom-Amiga Technologies GmbH PowerPC followers. Phase 5 was selling PowerPC accelerators for the Power Macintosh market. https://everymac.com/upgrade_cards/phase5/
---------
2. https://endoflife.date/raspberry-pi
Raspberry Pi 4 Model B ends on 01 Jan 2034.
Raspberry Pi CM4 ends on 01 Jan 2034.
Last edited by hammer; 16 July 2025 at 07:14.
pandy71
Location: PL?
#644 Posted on: 17 July 2025, 00:06
Quote:
Originally Posted by hammerAt first you can use lower latency mode on current PCIe - just use isochronous mode so latencies will be reduced.RP2040's PCIe would need to be upgraded for newer PCIe versions (lower latency), or improve RP2040's ARM Cortex M0+ @ 133 MHz with ARM Cortex A76 or higher e.g. Cortex A78C.
RP2040 is the 1st attempt to remove middleman Broadcom SoC IP dependency.
More complex CPU core means higher computational performance at a higher latency.
So interface frontend need to be served by simple CPU offering low latency not high computational performance.
Quote:
Originally Posted by hammerEverything is correct except one thing - BeagleBone Pocket 2 use AM6254 (quad-core A53 plus GPU) so performance is comparable to RPi4 at least, GPU performance is higher than BCM.@ https://www.ti.com/lit/sprace8
Ti AM335x Sitara SoC has ARM Cortex A8 up to 1 Ghz, which doesn't replace RPi 3A to 4B / CM4. https://www.ti.com/product/AM3358
Reminder, Buffee / TF1200 project uses Ti AM3358 with Cortex A8 @ 1 Ghz inside OSD3358 system on package.
The goal after RPi 4B / CM4 is to be better than ARM Cortex A72 while maintaining GPIO performance, not with a lower-tier Buffee / TF1200. The supply for RPi 3A+ / 3B and 4B / CM4 is not the issue.
RPi 3A+ Emu68 has no problems passing Buffee's Ti AM3358.
Quote:
Originally Posted by hammerPerhaps - this allow higher flexibility and performance.RPi 5 with RP2040 attached GPIO seems to be the transition phase towards RPi fat SoC attached GPIO.
My point was however not comparing RPi4 or RPi5 with other SoC's but show that RPi can have alternatives.
hammer
Location: Sydney/Australia
#645 Posted on: 18 July 2025, 07:11
Quote:
Originally Posted by pandy711. Michal Schulz already addressed RPi 5's unsuitability for Emu68 as an Amiga accelerator solution.At first you can use lower latency mode on current PCIe - just use isochronous mode so latencies will be reduced.
More complex CPU core means higher computational performance at a higher latency.
2. Reminder, RPi 4B and CM4 already have ARM Cortex A72.
Cortex A76 and A78 are the 4 instructions issued per cycle improvements from Cortex A72's 3 instructions issued per cycle.
PCIe 2.0 and 3.0 do not inherently have an "isochronous mode".
PCIe 5.0 has an isochronous mode.
https://forums.developer.nvidia.com/...r-gpu/285022/6
Code:
From NVIDIA Moderator, Date: March 19, 2024. "PCIe is not isochronous client, so there are no options to reduce latency or prioritize memory traffic from PCIe device."NVIDIA Blackwell with PCIe 5.0 was released in March 2025.
Quote:
Originally Posted by pandy71Michal Schulz already addressed RPi 5's unsuitability for Emu68 as an Amiga accelerator solution.So interface frontend need to be served by simple CPU offering low latency not high computational performance.
R2040's slow processing adds additional latency on top of the older PCIe's latency.
Emu68 is open source, do it yourself, prove it.
Quote:
Originally Posted by pandy71AM62xx family wasn't mentioned in your citedEverything is correct except one thing - BeagleBone Pocket 2 use AM6254 (quad-core A53 plus GPU) so performance is comparable to RPi4 at least, GPU performance is higher than BCM.
https://www.ti.com/lit/an/sprace8a/sprace8a.pdf
AM57x has dual ARM Cortex-A15.
AM65x has a quad ARM Cortex-A53, which RPi 3A+ and 3B already have ARM Cortex-A53.
Ti's CPU selection scope does not exceed RPi 3A+'s and 3B's ARM Cortex-A53 selection, let alone RPi 4B's and CM4's ARM Cortex A72.
RPi4 has ARM Cortex A72 which is far superior to ARM Cortex A53.
The Broadcom BCM2837B0 processor's quad-core ARM Cortex-A53, as found in the Raspberry Pi 3B+, has a 512KB L2 cache.
Quote:
Originally Posted by pandy71That's not progressing beyond RPi4's ARM Cortex A72 selection.Perhaps - this allow higher flexibility and performance.
My point was however not comparing RPi4 or RPi5 with other SoC's but show that RPi can have alternatives.
Last edited by hammer; 18 July 2025 at 07:32.
hammer
Location: Sydney/Australia
#646 Posted on: 18 July 2025, 12:35
Quote:
Originally Posted by Thomas RichterFor AmigaOS 1.3, Deluxe Music 2 has gadtools13.library. Workbench 2.x GUI look in AmigaOS 1.3.But users may not. The beauty of gadtools is (not only) the simplified interface. The beauty is that programs using it get a consistent look and feel, and a consistent GUI. This is important for usability. If you create custom gadgets (like everyone did in 1.2 and 1.3) you get the type of crappy programs you've seen under such kickstarts a lot. Like IconEdit. Not only crappy because the GUI wasn't well thought about, but also crappy because every program came with its own idea of how the GUI should look like. Compare 1.3 IconEdit with 1.3 "FED" (Font Editor). Totally different, totally irritating.
The "RKRM User Interface Style Guide" is an important book, and it is extremely helpful to create usable applications. Not only because it contains useful hints, but also because it ensures that all applications share a common look, and users feel "at home".
This was right from start an important feature of the Apple Macintosh (its strict requirements on user interface), CBM learned that relatively late, and gadtools is part of this idea. It is "the right way" of creating the user interface on AmigaOs, and the way that ensures the graphical design of your GUI fits to the rest of the system.
pandy71
Location: PL?
#647 Posted on: 20 July 2025, 00:25
Quote:
Originally Posted by hammerOther SoC's can be alternative.1. Michal Schulz already addressed RPi 5's unsuitability for Emu68 as an Amiga accelerator solution.
Quote:
Originally Posted by hammerFrom Amiga perspective difference will be insignificant - 10..15%?2. Reminder, RPi 4B and CM4 already have ARM Cortex A72.
Quote:
Originally Posted by hammerOnce again - gain from Amiga perspective probably will be insignificant.Cortex A76 and A78 are the 4 instructions issued per cycle improvements from Cortex A72's 3 instructions issued per cycle.
Quote:
Originally Posted by hammerUSB support isochronous mode. Even USB2 should be capable to deal with typical Amiga system.PCIe 2.0 and 3.0 do not inherently have an "isochronous mode".
PCIe 5.0 has an isochronous mode.
Quote:
Originally Posted by hammer2040 doesn't need to be fast in processing - you have DMA to deal with I/O.Michal Schulz already addressed RPi 5's unsuitability for Emu68 as an Amiga accelerator solution.
R2040's slow processing adds additional latency on top of the older PCIe's latency.
Quote:
Originally Posted by hammerlol you should have dog if you trying to play fetch game...Emu68 is open source, do it yourself, prove it.
FYI https://github.com/evansm7/pico-mac
Quote:
Originally Posted by hammerFunctionality stays similar for PRUAM62xx family wasn't mentioned in your cited
https://www.ti.com/lit/an/sprace8a/sprace8a.pdf
Quote:
Originally Posted by hammerGain from those differences will be not so significant and there is many various SoC's some of them are equipped with A5x some with A7x cores, there are also RISC-V SoC's.AM57x has dual ARM Cortex-A15.
AM65x has a quad ARM Cortex-A53, which RPi 3A+ and 3B already have ARM Cortex-A53.
Ti's CPU selection scope does not exceed RPi 3A+'s and 3B's ARM Cortex-A53 selection, let alone RPi 4B's and CM4's ARM Cortex A72.
RPi4 has ARM Cortex A72 which is far superior to ARM Cortex A53.
The Broadcom BCM2837B0 processor's quad-core ARM Cortex-A53, as found in the Raspberry Pi 3B+, has a 512KB L2 cache.
That's not progressing beyond RPi4's ARM Cortex A72 selection.
Location: Hastings, New Zealand
#648 Posted on: 20 July 2025, 03:27
Quote:
Originally Posted by hammerTranslation:- PiStorm 4 is plenty good enough.1. During the 16-bit era, the Amiga 500 kept up with mainstream game consoles with the 68000 selection e.g. Sega Mega Drive/ Genesis.
During the 32-bit era, 68EC020 to 68030 wasn't on par with low-cost ($15 to $20) MIPS 3050 (R3000A with embedded MMU). MIPS 3050 is a poor man's 68LC040-like 1 IPC CPU solution.
On the CPU front in modern times, RPi 4B or CM4's ARM Cortex A72 slightly exceeds Nintendo Switch 1's ARM Cortex A57. Both Cortex A72 and Cortex A57 are three-issue wide ARMv8A CPU designs. With PiStorm32 with CM4 or 4B, the CPU selection slightly exceeds a mainstream game console's CPU selection.
Quote:
Raspberry Pi 4 Model B ends on 01 Jan 2034.8.5 years away - same time the Amiga had under Commodore. I'll be 75 years old by then (if I live that long).
Raspberry Pi CM4 ends on 01 Jan 2034.
hammer
Location: Sydney/Australia
#649 Posted on: 21 July 2025, 06:58
Quote:
Originally Posted by pandy71Why? The Buffee/TF1200 project can cover alternative Ti SoCs.Other SoC's can be alternative.
Quote:
Originally Posted by pandy71RPi 3A+/3B+'s ARM Cortex A53 is a dual instruction issue per cycle in-order CPU design. RPi 3A+'s quad Cortex A53 cores have a unified 512 KB L2 cache.From Amiga perspective difference will be insignificant - 10..15%?
RPi 4B/CM4's ARM Cortex A72 is a three-instruction issue per cycle out-of-order CPU design. ARM Cortex A72 is directly based on ARM's larger Cortex A57 CPU core. RPi 4B / CM4s quad Cortex A72 cores have a unified 1MB L2 cache.
Cortex A53 = little core.
Cortex A57 = big core.
Emu68 with stock RPi 3A+ yields about Pentium II 300 or Celeron 300A level. It can be higher with a 1.6GHz overclock. The increased voltage can reach 1.8GHz overclock.
Emu68 with stock RPi 4B yields about a Pentium III 750 level. It can be higher with a +2GHz overclock, and can reach 3GHz with voltage increase and good cooling. My PiStorm32+RPi CM4 has a 2.1 GHz overclock without a voltage increase (warranty status is still ok). No problems rivaling 1.15Ghz SAM460ex or 1Ghz G4 AmigaOne XE(memory subsystem is rubbish).
Amiberry with RPi 5 (ARM Cortex A76) can brute force and beat the Emu68 + RPi CM4 (ARM Cortex A72) combo.
Quote:
Originally Posted by pandy71Wrong.Once again - gain from Amiga perspective probably will be insignificant.
I have RPi 3A+, RPi 4B and RPi CM4.
Quote:
Originally Posted by pandy71Prove it.USB support isochronous mode. Even USB2 should be capable to deal with typical Amiga system.
In USB 2.0, isochronous transfers, designed for real-time data like audio and video, have a latency of 1 millisecond (ms) for Full Speed and 125 microseconds (µs) for High Speed.

The requirement is nanosecond range, NOT microseconds.
1 microsecond = 1000 nanoseconds
-------------------
Quote:
Originally Posted by Bruce AbbottFor PiStorm32's current release, RPi 4B / CM4 is enough, but the planning is for "next gen" releases.Translation:- PiStorm 4 is plenty good enough.
The original 16-bit PiStorm CPLD officially supports RPi 3A+ and Zero 2. RPi 4B can work, but not guaranteed. My original 16-bit PiStorm CPLD "Rev B Max II" is working with RPi 4B.
The incoming PiStorm16 FPGA officially supports up to RPi CM4.
If the Amiga platform is properly backed by better-funded investors, it should be ARM. PowerPC e5500 @ 1.4Ghz/T1040's 170 euros are too expensive for a modern A500-style reboot. Looking at the Nintendo Switch 2 hardware level.
Last edited by hammer; 21 July 2025 at 08:21.
Promilus
Location: Poland
#650 Posted on: 21 July 2025, 18:14
Quote:
From Amiga perspective difference will be insignificant - 10..15%?Is that the same between A53 vs A72 PiStorm? No it is not. So why do you assume it suddenly will come to barely noticeable in A76 vs A72 when runnin 68k JIT?
pandy71
Location: PL?
#651 Posted on: 22 July 2025, 01:16
Quote:
Originally Posted by hammerMy point was NOT on particular product but on general principle - there are multiple SoC's with capabilities same or better than those from BCM.Why? The Buffee/TF1200 project can cover alternative Ti SoCs.
TI SoC's equipped with PRU may replace FPGA/CPLD in software.
Other SoC's need some FPGA/CPLD to interface with 68k bus.
Quote:
Originally Posted by hammerOnce again - you are bonded to one, particular SoC family from BCM and one family of products based around BCM SoC's.RPi 3A+/3B+'s ARM Cortex A53 is a dual instruction issue per cycle in-order CPU design. RPi 3A+'s quad Cortex A53 cores have a unified 512 KB L2 cache.
RPi 4B/CM4's ARM Cortex A72 is a three-instruction issue per cycle out-of-order CPU design. ARM Cortex A72 is directly based on ARM's larger Cortex A57 CPU core. RPi 4B / CM4s quad Cortex A72 cores have a unified 1MB L2 cache.
Cortex A53 = little core.
Cortex A57 = big core.
Emu68 with stock RPi 3A+ yields about Pentium II 300 or Celeron 300A level. It can be higher with a 1.6GHz overclock. The increased voltage can reach 1.8GHz overclock.
Emu68 with stock RPi 4B yields about a Pentium III 750 level. It can be higher with a +2GHz overclock, and can reach 3GHz with voltage increase and good cooling. My PiStorm32+RPi CM4 has a 2.1 GHz overclock without a voltage increase (warranty status is still ok). No problems rivaling 1.15Ghz SAM460ex or 1Ghz G4 AmigaOne XE(memory subsystem is rubbish).
Amiberry with RPi 5 (ARM Cortex A76) can brute force and beat the Emu68 + RPi CM4 (ARM Cortex A72) combo.
Wrong.
I have RPi 3A+, RPi 4B and RPi CM4.
But there are others SoC's offering other options, also higher clock and perhaps better memory subsystem - search for benchmarks - RPi solutions are not the best ones - they are OK - definitely most popular - that's all.
Quote:
Originally Posted by hammeryeah, and 1000000 picoseconds...Prove it.
In USB 2.0, isochronous transfers, designed for real-time data like audio and video, have a latency of 1 millisecond (ms) for Full Speed and 125 microseconds (µs) for High Speed.
The requirement is nanosecond range, NOT microseconds.
1 microsecond = 1000 nanoseconds
-------------------
Seem you are confused - you need some FPGA/CPLD to interact with real 68k bus so this part can be transparent from SoC perspective.
You have like 48..56 I/O's at least to deal with - you need some frontend for such complex SoC's like modern ARM based - I/O latency, interrupt overhead etc.
That's why you can create frontend and link it with some general I/O interface such as USB / PCIe - some real time CPU like PRU or XMOS or perhaps even programmable state machine may be substitute for FPGA/CPLD shifting paradigm form HW to SW. Also it may be cheaper and more flexible in overall than FPGA/CPLD. For example it may offer some preprocessor for 68k ISA.
Quote:
Originally Posted by hammerGood to know - but still - this shows opportunity to relief dependency form single SoC vendor / single SBC vendor.For PiStorm32's current release, RPi 4B / CM4 is enough, but the planning is for "next gen" releases.
The original 16-bit PiStorm CPLD officially supports RPi 3A+ and Zero 2. RPi 4B can work, but not guaranteed. My original 16-bit PiStorm
Quote:
Originally Posted by hammerThere are multiple possibilities - even company similar to Transmeta with idea similar to Code MorphingIf the Amiga platform is properly backed by better-funded investors, it should be ARM. PowerPC e5500 @ 1.4Ghz/T1040's 170 euros are too expensive for a modern A500-style reboot. Looking at the Nintendo Switch 2 hardware level.
hammer
Location: Sydney/Australia
#652 Posted on: 22 July 2025, 04:10
Quote:
Originally Posted by PromilusIt's still noticeable between A72 vs A76 due to major differences that matters for 68K emulation.Is that the same between A53 vs A72 PiStorm? No it is not. So why do you assume it suddenly will come to barely noticeable in A76 vs A72 when runnin 68k JIT?
For RPi 4's Cortex A72 vs RPi 5's Cortex A76
1. A72's shared 1MB L2 cache vs A76's shared 2MB L2 cache.
2. A72's three instruction issues per cycle vs A76's four instruction issues per cycle.
A76 core can properly duplicate CISC's two operations with an ALU+memory operand for each operation.
CISC ALU with memory operand is an implied data load from memory. RISC load is an explicit load data from memory. CISC has an advantage in fused instructions.
Apple M series solved this X86/68K CISC advantage with many instruction issue slots e.g.
8 instruction issues per cycle per thread with M1,
9 instruction issues per cycle per thread with M3.
10 instruction issues per cycle per thread with M4.
ARM is following Apple's lead e.g. ARM Cortex X1 has 5 decoders, Cortex X3 has 6 decoders, Cortex X4 has 10 decoders.
AMD Zen 5 recently doubled its four x86 CISC decoders to eight X86 decoders. The large X3D L3 cache exposes Zen 5 IPC's gains since IOD wasn't improved from Zen 4.
Intel Raptor Cove has 6 x86 CISC decoders.
Intel Lion Cove (for Arrow Lake, Luna Lake) has 8 x86 CISC decoders. Intel needs to fix Lion Cove's cache latency flaws.
Intel Skymont has 9 x86 CISC decoders, but the backend units doesn't match the front-end capabilities. Intel has 9 x86 CISC decoders foundation.
CISC horizontal scaling is harder than RISC. CISC camp needs to increase evolution pace.
The selection for ARM with the Amiga is due to ARM's big endian mode.
ARM camp left PowerPC for dead.
3.A76's 64KB + 64 KB of L1 cache per core vs A72's 48KB + 32 KB of L1 cache per core.
hammer
Location: Sydney/Australia
#653 Posted on: 22 July 2025, 04:14
Quote:
Originally Posted by pandy71Cite a cheap Ti SoC with better than RPi 4's Cortex A72.My point was NOT on particular product but on general principle - there are multiple SoC's with capabilities same or better than those from BCM.
TI SoC's equipped with PRU may replace FPGA/CPLD in software.
Other SoC's need some FPGA/CPLD to interface with 68k bus.
Quote:
Originally Posted by pandy71That's just noise.Once again - you are bonded to one, particular SoC family from BCM and one family of products based around BCM SoC's.
But there are others SoC's offering other options, also higher clock and perhaps better memory subsystem - search for benchmarks - RPi solutions are not the best ones - they are OK - definitely most popular - that's all.
Quote:
Originally Posted by pandy71You're confused. Go argue against Michal Schulz and Claude. Claude has identified PCI 3.0's 125 ns improvement as path way for RPi 5.Seem you are confused - you need some FPGA/CPLD to interact with real 68k bus so this part can be transparent from SoC perspective.
You have like 48..56 I/O's at least to deal with - you need some frontend for such complex SoC's like modern ARM based - I/O latency, interrupt overhead etc.
Last edited by hammer; 22 July 2025 at 04:23.
Location: Hastings, New Zealand
#654 Posted on: 22 July 2025, 09:00
Quote:
Originally Posted by hammerPathetic. We barely have CM4 and Amiga fans already want more. When will it end?For PiStorm32's current release, RPi 4B / CM4 is enough, but the planning is for "next gen" releases.
Quote:
The original 16-bit PiStorm CPLD officially supports RPi 3A+ and Zero 2. RPi 4B can work, but not guaranteed. My original 16-bit PiStorm CPLD "Rev B Max II" is working with RPi 4B.If it works it's good enough - better than Amiga accelerator cards often used to be back in the day!
Quote:
The incoming PiStorm16 FPGA officially supports up to RPi CM4.Good news. I might look at getting one just for fun.
Quote:
If the Amiga platform is properly backed by better-funded investors, it should be ARM. PowerPC e5500 @ 1.4Ghz/T1040's 170 euros are too expensive for a modern A500-style reboot.I agree. RPi has everything we need including volume production. Other similar SoC's could do the job too. PPC is only of interest to OS4 fans.
hammer
Location: Sydney/Australia
#655 Posted on: Yesterday, 10:29
Quote:
Originally Posted by Bruce AbbottIt's MAGA i.e. Make Amiga Great Again.Pathetic. We barely have CM4 and Amiga fans already want more. When will it end?

Releasing "not-so-latest" ARM hardware works for Nintendo. Why not the Amiga?
Emu68 method is cheaper than the full ASIC 68080 pathway.
Quote:
Originally Posted by Bruce AbbottUnlike the original PiStorm CPLD, the incoming PiStorm16 FPGA shares a common codebase with PiStorm32 FPGA. It's easier software maintenance.If it works it's good enough - better than Amiga accelerator cards often used to be back in the day!
https://amitopia.com/pistorm16-for-a...a-masterpiece/
PiStorm16 firstly targets A600 since RPi CM4's small size fits better for the A600.
[ Show youtube player ]
Emu68-Pistorm16 (Beta V1.0.4_delay23 - 20.04.25) with RPi CM4 and A600 is operational, playing games.
The original PiStorm CPLD has a few revisions.
I don't have an A600, but Emu68-PiStorm16-RPi CM4 should benefit A600 owners.
Quote:
Originally Posted by Bruce AbbottBig-endian mode 32 GPR PPC can be emulated on big-endian mode 32 GPR ARMv8. Less overheads when compared to little-endian 16 GPR X86-64 efforts.I agree. RPi has everything we need including volume production. Other similar SoC's could do the job too. PPC is only of interest to OS4 fans.
It's possible to emulate CyberStorm PPC / Blizzard PPC since WinUAE has CyberStorm PPC / Blizzard PPC emulation since Musashi is based on UAE's 68K emulation codebase. WinUAE recycles Qemu's PPC emulator.
Also, PowerPC pathway allows for SIMD 128-bit Altivec to SIMD 128-bit NEON translation since the standard 68K doesn't have SIMD extensions.
Fat ARM64 and fat X86-64 CPUs have an advantage in volume production.
Last edited by hammer; Yesterday at 11:01.
pandy71
Location: PL?
#656 Posted on: Yesterday, 23:37
Quote:
Originally Posted by Bruce AbbottI agree. RPi has everything we need including volume production. Other similar SoC's could do the job too. PPC is only of interest to OS4 fans.
It has poor 3D without chance to be fully open source (means no chance for native Amiga drivers). Video decoder in BCM is master ruler of the whole SoC and it is not open sourced at all.
Last edited by pandy71; Yesterday at 23:51.
pandy71
Location: PL?
#657 Posted on: Yesterday, 23:50
Quote:
Originally Posted by hammerWhy TI? You have CPLD/FPGA to interface with 68K bus so you don't need PRU - PRU can be alternative to CPLD/FPGA.Cite a cheap Ti SoC with better than RPi 4's Cortex A72.
RockChip offers better than BCM SoC's (for example better 3D and video decoding).
Quote:
Originally Posted by hammerNoise is approx 75% of content you produce - please don't complain on noise - (i'm still not convinced if you are human or some AI driven weird bot).That's just noise.
Quote:
Originally Posted by hammerNope, i'm not confused - but you are for sure - way how you argument sounds like AI chat bot (long time asked you on this and never get legible answer) - it is like in those german fairy tales where there is some bad kobold doing weird things to people.You're confused. Go argue against Michal Schulz and Claude. Claude has identified PCI 3.0's 125 ns improvement as path way for RPi 5.
Are you a HUMAN ? Don't get me wrong but we are leaving in funny times so i prefer to ask and not to perform endless discussions with AI driven chat bot. (btw Asimov robotic laws extrapolate on AI so don't lie!) If you are AI driven bot (so virtual robot) then such conversation hurting me virtually i.e. violate first law of robotics.
Location: Munich/Bavaria
#658 Posted on: Today, 00:24
Quote:
Originally Posted by pandy71The Videocore can be used without Linux:It has poor 3D without chance to be fully open source (means no chance for native Amiga drivers). Video decoder in BCM is master ruler of the whole SoC and it is not open sourced at all.
https://ultibo.org
(Pascal/Lazarus bare metal environment with support for "OpenGL ES with hardware acceleration")
https://www.lse.epita.fr/lse-summer-...darius-gpu.pdf
(Mini OpenGL API without X via Mailbox Interface)
https://macoy.me/blog/programming/PiGPU
[ Show youtube player ]
(Hacking the Raspberry Pi's VideoCore IV GPU)
grelbfarlk
Location: USA
#659 Posted on: Today, 04:39

