G4 Karbo

G4 Karbo
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Michael Karbo and ELI Aps., Denmark, Europe.
Instructions
have to be decoded, and not least, executed , in the CPU. I won’t go into
details on this subject; it is much too complicated. But I will describe a few
factors which relate to the execution of instructions. My description has been
extremely simplified, but it is relevant to the understanding of the microprocessor.
This chapter is probably the most complicated one in the guide – you have been
warned! It’s about:
If we continue to focus on speeding up the processor’s work, this
optimisation must also apply to the instructions – the quicker we can shove
them through the processor, the more work it can get done.
As
mentioned before, instructions are sent from the software and are broken down
into micro-ops (smaller sub-operations) in the CPU. This decomposition
and execution takes place in a pipeline .
The
pipeline is like a reverse assembly line. The CPU’s instructions are broken
apart (decoded) at the start of the pipeline. They are converted into small
sub-operations ( micro-ops ), which can then be processed one at a time in
the rest of the pipeline:
The pipeline is made up of a number stages . Older processors have
only a few stages, while the newer ones have many (from 10 to 31). At each
stage “something” is done with the instruction, and each stage requires one
clock tick from the processor.
Modern CPU’s have more than one pipeline, and can thus process several
instructions at the same time. For example, the Pentium 4 and AthlonXP can decode
about 2.5 instructions per clock tick.
The first Pentium
4 has several very long pipelines, allowing the processor to hold up to 126
instructions in total, which are all being processed at the same time ,
but at different stages of execution (see Fig.
88. It is thus possible to get the CPU to perform more
work by letting several pipelines work in parallel:
Instructions
executed
at the same time

Intel
Pentium 4
(first generation)

Figure 88. By making use of more, and longer, pipelines, processors can execute
more instructions at the same time.
One might
imagine that the engineers at Intel and AMD could just make even more parallel
pipelines in the one CPU. Perhaps performance could be doubled? Unfortunately
it is not that easy.
It is not
possible to feed a large number of pipelines with data. The memory system is
just not powerful enough. Even with the existing pipelines, a fairly large
number of clock ticks are wasted. The processor core is simply not utilised
efficiently enough, because data cannot be brought to it quickly enough.
Another
problem of having several pipelines arises when the processor can decode
several instructions in parallel – each in its own pipeline. It is impossible
to avoid the wrong instruction occasionally being read in (out of sequence).
This is called misprediction and results in a number of wasted clock
ticks, since another instruction has to be fetched and run through the
“assembly line”.
Intel has
tried to tackle this problem using a Branch Prediction Unit , which
constantly attempts to guess the correct instruction sequence.
The number
of “stations” ( stages ) in the pipeline varies from processor to
processor. For example, in the Pentium II and III there are 10 stages, while
there are up to 31 in
the Pentium 4.
In the
Athlon, the ALU pipelines have 10 stages, while the FPU/MMX/SSE pipelines have
15.
The longer
the pipeline, the higher the processor’s clock frequency can be. This is
because in the longer pipelines, the instructions are cut into more (and hence
smaller) sub-instructions which can be executed more quickly.
Figure 89. Higher clock frequencies require
long “assembly lines” (pipelines).
Note that the two AMD processors have different pipeline lengths for
integer and floating point instructions. One can also measure a processor’s efficiency
by looking at the IPC number ( Instructions Per Clock ), and AMD’s Athlon
XP is well ahead of the Pentium 4
in this regard. AMD’s Athlon XP processors are actually
much faster than the Pentium 4’s at equivalent clock frequencies.
The same is
even more true of the Motorola G4 processors used, for example, in Macintosh
computers. The G4 only has a 4-stage pipeline, and can therefore, in principle,
offer the same performance as a Pentium 4, with only half the clock frequency
or less. The only problem is, the clock frequency can’t be raised very much
with such a short pipeline. Intel have therefore chosen to future-proof the
Pentium 4 by using a very long pipeline.
What is
it that actually happens in the pipeline? This is where we find the so-called
execution units. And we must distinguish between to types of unit:
If the processor has a brain, it is the ALU unit. It is the calculating
device that does operations on whole numbers ( integers ). The computer’s
work with ordinary text , for example, is looked after by the ALU.
The ALU is
good at working with whole numbers. When it comes to decimal numbers and
especially numbers with many decimal places ( real numbers as they are
called in mathematics), the ALU chokes, and can take a very long time to
process the operations. That is why an FPU is used to relieve the load. An FPU
is a number cruncher, specially designed for floating point operations.
There are
typically several ALU’s and FPU’s in the same processor. The CPU also has other
operation units, for example, the LSU ( Load/Store Unit ).
Look again at Fig. 73. You can see that the processor core is right beside
the L1 cache. Imagine that an instruction has to be processed:
This description applies to the working cycle in, for example, the
Pentium III and Athlon. As a diagram it might look like this:
But the way the relationship between the pipeline and the execution
units is designed differs greatly from processor to processor. So this entire
examination should be taken as a general introduction and nothing more.
In the
Pentium 4, the instruction cache has been placed between the “Instruction
fetch/Translate” unit (in Fig.
90 and the ALU/FPU. Here the instruction cache ( Execution
Trace Cache ) doesn’t store the actual instructions, but rather the
“half-digested” micro-ops.
The actual pipeline in the Pentium 4 is longer than in other CPU’s; it
has 20 stages. The disadvantage of the long pipeline is that it takes more
clock ticks to get an instruction through it. 20 stages require 20 clock ticks,
and that reduces the CPU’s efficiency. This was very clear when the Pentium 4
was released; all tests showed that it was much slower than other processors
with the same clock frequency.
At the same
time, the cost of reading the wrong instruction ( misprediction ) is much
greater – it takes a lot of clock ticks to fill up the long assembly line
again.
The Pentium
4’s architecture must therefore be seen from a longer-term perspective. Intel
expects to be able to scale up the design to work at clock frequencies of up to
5-10 GHz. In the “ Prescott ”
version of Pentium 4, the pipeline was increased further to 31 stages.
AMD’s 32
bit Athlon line can barely make it much above a clock frequency of 2 GHz, because
of the short pipeline. In comparison, the Pentium 4 is almost ”light years”
ahead.

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The contest is over and we have our three winners :judge: :dance: I have to apologize, the voting system was a bit messy and not the most secure out there. The strawpoll site was not working and was still unusable three days later as far as I'm concerned o.o So our three final winners are : -Vivian in first place ! It's a large and rather expected win :winner: ( To be honest I would probably have been in trouble otherwise ! XD) -Anko scores a very honorable second place with a lot of votes. More reasons for her to be smug :D -And Anna made it third after an intense battle with Crisis ! Not totally sure the grumpy naga herself is thrilled about that result but well XD Congrats to the three winners ! They gained some bragging rights and yes, there will be a victory picture ;) And thank you guys for your votes !
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On much lighter news, the Felarya defense game just got a new update ! https://aryion.com/forum/viewtopic.php?f=79&t=60775&start=140 and this is a big one ! It adds a whole new level with a really neat game mechanic and three new preds including two certain ladies with long tongues and a new cut scene featuring one of them XP What i especially liked here is how the game ramp up in difficulty ^^ Previous levels were tricky in their own ways but personally I managed to pass them once I found a strategy that worked with my style of play and sticked with it. However that new level is clearly harder and tell you to carefully consider the tools at your disposal and consider using things you might have overlooked before. It makes finding your own solution all the more satisfying. This is very appreciable in a tower defense game :3 I can only recommend to you to check it if you haven't already ! Yes it's a vore game but besides the vore, there is a surprisingly unique and well
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You might wonder why i didn't post anything in a while.. The answer is I'm just not in the mood ^^; I'm.. tired, anxious, full of worries I have trouble to sleep and I don't have very productive days, checking constantly the news about Russia's invasion of Ukraine and the enormous shockwaves it caused across the world... I'm a slightly anxious person even in normal times but nowadays it's of the chart. We went from a pandemic to rather credible risks of WW3 :/ Things seem to be spiraling a bit out of control right now, to go too fast. One momentous event follow the other, like we entered one of these part of History everyone will read about in the future but instead of reading it, we're living it... I really wish all of you guys to be safe. And if any of you guys is from Ukraine, you have my deepest sympathy and also my admiration and respect. You are showing to the rest of the world what it's like to fight for your freedom but your people is also paying a terrible price for
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If you feel generous and you want to support me and my work, please check my Patreon page:
You can become my patron and in return you get to see future pictures in progress way before they hit the internet, make suggestions on what I should draw next and other cool stuff X3
It's in construction for now but I'll also be present on subscribestar soon: https://subscribestar.adult/karbo
My comics are available on E.junkie : https://karbo.e-junkie.com/
Slightly weird question, sorry to bother you with it, but I think I'm not the only one wondering. Do the majority of the Felarya characters get aroused by vore, or is it mostly just Mennysan, Chals, and Vivian? I remember you saying somewhere before that Crisis only values it as food satisfaction.
Will you ever do a tome 6 of your Felarya Manga ? Or you won't continue this story ?
Would love to know what happen next ! ^^
Felarya Mouth contest roster predictions:
can i talk about what to do for art trades, please be you busy i'm sorry man
do you have a size comparison sheet of the different sized preds and prey?

Tome 1 of the Felarya manga

Felarya is a jungle world, full of wonders, fantastic treasures and giant, voracious predators. The naga Crisis is one of them, despite also being a kind, cheerful girl. Meet her and some other inhabitants in the first Felarya manga! Contains mature content (nudity) and soft vore (creatures/people being devoured whole and alive). The manga is 55 pages long.

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Check and mate
USD 10.00

Hard Choices
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A princess'duty
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Felarya Manga tome5
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Felarya manga tome4
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Introducing Crisis, the giant, cheerful but voracious naga. The manga is 55 pages long.

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