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* This module defines the various instructions that exist within the language.
* This data type represents all of the instructions that can occur in
* the language. It also contains a "val" instruction which encapsulates
* data that can be stored in the store.
* It's called "tm" because tm is short for "term" which is what the basic
* element of most small-step semantics are called.
* This machine has a single register and has memory addressing modes.
* val : Represents a value in memory
* sec : Represents a secret value in memory
* ldi : Load immediate value into register
* lda : Load value from specified address into register
* sta : Store value in register into specified address
* add : Add a constant value to the value in the register. The result stays
* map : Add a TLB entry to the MMU.
* invalidate : Reset a TLB entry back to a default value.
* jmp : Jump to the address located in the register.
* jeq : Jump to the specified address if the register is zero.
* jne : Jump to the specified address if the register is negative.
* trap: Generate a machine trap (syscall, exception, or interrupt).
* svaDeclareStack : Declare a range of memory to be a stack.
* svaLoadPGTable : Load the ASID value
* svaInitStack : Create and initialize a new thread
* svaSwap : Switch to a new thread identified in the register
* svaRegisterTrap: Register a trap handler
* svaSaveIcontext: Save a copy of the interrupt context
* svaLoadIcontext: Save a copy of the interrupt context
* svaPushFunction: Push a function frame on to the interrupted stack
* jsr : Jump to the subroutine located in the register.
* ret : Return to the previously executed jsr instruction.
| svaDeclareStack : nat -> nat -> tm
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* Prove that a simple CFI policy is maintained for the semantics of our
(* Load Coq Standard Library modules *)
Require Import Coq.Logic.Classical_Prop.
* This theorem proves that if a thread list is valid, then any thread
Theorem threadIsValid: forall (cfg : list nat) (mmu : MMU) (ds : store) (tl : ThreadList) (n : nat),
validThreadList tl cfg mmu ds -> validThread (getThread n tl) cfg mmu ds.
assert (validThreadList (a :: tl) cfg mmu ds).
* Prove that the program counter always moves to the next instruction
* or is changed to a value that is within the list of acceptable
Theorem cfisafe : forall c1 c2 : config,
(validThreadList (getThreadList c1) (getCFG c1) (getCMMU c1) (getStore c1)) /\
((vlookup (minus (getPC c2) 1) c2) = svaSwap) \/
((getPC c2) = (getICPC (itop (getThreadICList (getCurrThread c1) (getThreadList c1))))).
(* Addition to case 8: jeq fallthrough *)
(* Addition to case 9: jne fallthrough *)
assert (validThread (getThread vr tl) CFG MMU DS).
* Prove that the program counter always moves to the next instruction
* or is changed to a value that is within the list of acceptable
Theorem cfisafe2 : forall c1 c2 : config,
(validThreadList (getThreadList c1) (getCFG c1) (getCMMU c1) (getStore c1)) /\
(In (getThread (getCurrThread c1) (getThreadList c1)) (getThreadList c1)) /\
(AreAllThreadICsInText (getThreadList c1) (c1)) /\
(AreAllThreadSICsInText (getThreadList c1) (c1)) /\
(threadListInText (getThreadList c1) (getCFG c1) (getCMMU c1)
(getTextStart c1) (getTextEnd c1)) /\
((vlookup (minus (getPC c2) 1) c2) = svaSwap) \/
((vlookup (minus (getPC c2) 1) c2) = trap) \/
(* Addition to case 8: jeq fallthrough *)
(* Addition to case 9: jne fallthrough *)
assert (validThread (getThread vr tl) CFG MMU DS).
assert (goodPCICL (getThreadICList tid tl) CFG MMU DS).
* Prove that fetching an instruction through a virtual address never changes
* even though stores can modify physical memory and the MMU can remap pages.
Theorem NXText : forall (c1 c2 : config)
(getTextStart c1) <= (getPhysical (getTLB v (getCMMU c1))) <= (getTextEnd c1) /\
-> (vLookup v (getCMMU c1) (getStore c1)) =
(vLookup v (getCMMU c2) (getStore c2)).
(* Prove that several properties hold on the final configuration *)
(* Prove by induction on the proof tree *)
* Need to show that the two physical addresses must be different. This is
* because the address written cannot be in the text segment while the address
* checked is within the text segment. The address written cannot be within
* the text segment because the text segment is not writeable.
assert (getPhysical (getTLB v MMU) <> getPhysical (getTLB n MMU)).
(* Detour: show that v is not writeable *)
(* Back from detour: show that the two physical addresses must be different *)
(* Resume the proof of induction case 3 *)
(* Case: getPhysical (getTLB v0 MMU) < cs *)
(* Case: ce < getPhysical (getTLB v0 MMU) *)
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KCoFI Pudding: The formal proofs for the KCoFI system - Pudding/Instructions.v at master · jtcriswell/Pudding
KCoFI Pudding: The formal proofs for the KCoFI system - Pudding/SVAOS.v at master · jtcriswell/Pudding
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