Bbc Tube

Bbc Tube




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Bbc Tube
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From Wikipedia, the free encyclopedia

^ Jump up to: a b Acorn Application Note 004, "Tube Application Note"

^ Although the most commonly-cited reason for software running faster on the second processor was it can offload I/O tasks such as graphics-drawing computations to the host processor, a much more important consideration was clock speed: the host processor was limited to 2MHz to allow time for VDU-refresh to access the RAM, whereas the coprocessor could run at 3MHz, with a much simpler DRAM refresh stalling it at 68kHz, see pages 7 and 19 of the 6502 Second Processor Service Manual archived at http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_65022ndprocSM.pdf

^ Watford Electronics,"Advanced Reference Manual for the BBC Master Series",1988

^ Coll, John (1982) [1982]. Allen, David (ed.). The BBC Microcomputer User Guide (zipped RTF) . London: British Broadcasting Corporation. pp. 443, 450, 473. ISBN 0-563-16558-8 . Retrieved 25 January 2010 .


In computing, the Tube was the expansion interface and architecture of the BBC Microcomputer System which allowed the BBC Micro to communicate with a second processor , or coprocessor .

Under the Tube architecture, the coprocessor would run the application software for the user, whilst the Micro (acting as a host ) provided all I/O functions, such as screen display, keyboard and storage devices management. A coprocessor unit could be coldplugged into any BBC Micro with a disk interface (whose ROM contained the necessary host software) and used immediately.

The 40-pin IDC "Tube" connector was a simple slave connection to the host processor's main bus, with 8 data lines, 7 address lines, and an interrupt input. The Tube protocols were implemented by hardware in the attached device.

Inside the coprocessor unit a proprietary chip (the Tube ULA , manufactured initially by Ferranti ) interfaced and logically isolated the host and coprocessor buses . This allowed the Tube to work with a completely different bus architecture in the coprocessor unit. The only other active components needed were a microprocessor , some RAM , a small ROM containing processor specific client code, glue logic such as an address decoder and a power supply .

The two processors communicated through four pairs of FIFO buffers in the Tube ULA. Console input/output, error messages , data transfers and system calls each had their own pair of buffers, one for each direction. The queue capacity varied between 1 and 24 bytes, depending on the dedicated buffer function. Each buffer had a control register and status register to monitor its state and configure the raising of interrupts .

The protocol for the use of these buffers was rigorously specified by Acorn Computers [1] and amounts to interprocess communication by message passing . Most interaction was asynchronous but fast block transfers were synchronous and consisted of the ho
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